Karnaugh Maps (Digital Logic Optimization)
David A. Snyder, P.E.
This 6 PDH course shows how to rearrange a truth table into a Karnaugh map and how to derive an optimum logical expression from the Karnaugh map. It is important to optimize (reduce and simplify) the digital function in order to do away with extraneous, unnecessary logic components that add cost and complexity to the design without providing any benefit. The concepts of minterms (sum of products) and maxterms (product of sums) will be explained and the use of both will be illustrated. The concept of “don’t care” conditions will be discussed, and the effects of these conditions on the optimization of the logical functions will be clearly demonstrated. Many illustrations and several examples are given to increase the reader’s understanding of the subject matter.
This course includes a multiple-choice quiz at the end, which is designed to enhance the understanding of the course materials.
The following learning objectives are included in this course:
Anyone who is involved in the design of relay logic (such as control panels) or gate logic (such as electronic circuit boards) will benefit from this course.
Benefit for Attendee
Upon successful completion of the course, the reader will have a thorough understanding of the use of Karnaugh maps to determine an optimum logical expression of a given digital (binary) function. This function could be described by a truth table or as a binary equation, in the form of minterms (sum of products) like x + x’y + yz’, or in the form of maxterms (product of sums) like (x+y)(x’+z)(x+y’+z’).
A truth table is one means of defining the output requirements of a digital (binary) function, based on all of the possible input conditions. The truth table assigns a value of 1 (true or on) or 0 (false or off) to the output of each unique combination of input variables. A Karnaugh map rearranges the information presented in the truth table such that cells with a value of 1 can be grouped together if they are logically adjacent to each other. This grouping will reveal which of the input variables can be ignored, since they aren’t required to implement the digital function. This technique works the same way when grouping together cells that have a value of 0. When the optimized function has been extracted from the Karnaugh map, it can be used to design gate logic or relay logic that uses fewer components than would have been required if only the truth table were used to design the logic. Several examples of the results of optimization are presented in this course, as well as the concept of “don’t care” conditions and the resulting further optimization that can be realized.
The course content is in the following PDF file:
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Digital (binary) logic is being designed every day in the form of relay logic (in control panels, switchgear, and automobiles) and gate logic (integrated circuits on circuit boards, in computers, in televisions, and also in automobiles.). The concepts presented in this course are used to optimize the design of that logic by reducing the required number of components (relay contacts or integrated circuit chips), as well as reducing the amount of interconnecting wiring. This optimization reduces the cost, size, and complexity of projects and products.